FFs thus contribute a significant portion of gate count to the overall system design.
In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as register file and shift register. Introductionįlip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. Postlayout simulations in TSMC 1P6M 0.18 μm CMOS process model also indicate that the proposed design is as efficient as its single-mode counterpart in various performance metrics. Due to the novelty in pulse generator design, the layout area overhead is only 8% when compared with other single-mode counterpart design. It supports both single-edge- and double-edge-triggered operations subject to a mode select control. A low complexity dual-mode pulse-triggered FF design for wireless baseband processing is presented in this paper.
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